Displacement measuring apparatus

ABSTRACT

A tape rule or other displacement measuring apparatus comprises a reader means and a member that are relatively movable. The member carries a position track defined by a sequence of alternative markings made in succession along the member. The alternative markings record different values in a pseudo-random sequence which is the result of repetitive operations on a seed consisting of a small number of elements. The sequence has the property that a group of successive markings of length at least equal to that of the seed occurs at a single position in the sequence so that a succession of markings read from the track and of length at least equal to the seed defines an absolute position of the reading means and the member. The reading means has at least three sensors arranged to respond to different locations within each marking with the pattern of the markings and the location of the sensors arranged so that only a single sensor changes state each time that the member moves through an interval of displacement relatively to the sensing means. The states occur consecutively in alternative sequences along the member that are recognizable by decoding logic fed with successive states as a logical value corresponding to one of the alternative markings depending upon which sequence has been followed.

FIELD OF THE INVENTION

This invention relates to displacement measuring apparatus andparticularly, though not exclusively, to a tape rule.

BACKGROUND TO THE INVENTION

It is known, e.g., from Patent Specification Nos. U.S. Pat. No.4,162,781; GB-A-2056660 and GB-A-1571245 to read optical markings on atape rule and derive therefrom information about the position of thetape. If only movement and direction are required to be known, then onlytwo photosensors are required. A workable tape system can be made usingthis approach and an implementation of it is described in U.S. Pat. No.-4,161,781. In essence, such an arrangement counts output statetransitions as the tape moves from a known position to an unknownposition whose displacement is to be measured. But positional accuracyrelies on accurate and reliable knowledge of the first position and onaccurate transition counting. Should any error occur in counting duringa movement, as a result of damage to the line of marks being counted,then subsequently the known position will be in error, and the tape as awhole will be useless.

A method and apparatus for determining the absolute position of amovable element mounted for movement along a path is described in U.S.Pat. No. 4,009,377 (Elms) and is based on the development of apseudo-randum sequence of indicia that uniquely define the position ofthe movable element on the path. But the provision of a separate timingtrack is essential and errors in reading the timing track would resultin spurious detected indicia and large errors in measured position fromwhich recovery would be difficult. The use of binary sequences toaddress sections of a rotating device is described by B. Arazi,Electronics Letters, 20, 61-62 (19 Jan. 1984).

SUMMARY OF THE INVENTION

It is an object of the invention to provide a tape rule or otherdisplacement measuring device in which an accurate measurement ofcurrent tape position can be deduced irrespective of whether or not thefirst position of the tape was known, and that is robust to erasure orfailure to measure accurately some of the tape markings between theinitial and the current tape positions. It is a further object of theinvention to provide a displacement measuring device having amultiplicity of sensors responsive to different areas of a spatial codetrack of the tape, wherein an absolute tape position can be deduced fromthe code by analysis of a sequence of sensor output states brought aboutby tape movement.

Broadly stated the invention provides displacement measuring apparatuscomprising a member having marks and spaces occurring along a positiontrack and defining encoded opsitions, sensing means past which themember moves arranged to read marks and spaces from the position track,and decoding logic fed with the output of the sensing means and arrangedto derive a tape position from sensed and decoded information from theposition track. The use in a tape rule of a position track carryingencoded information that is not simply counted is believed to be new.

The invention therefore provides displacement measuring apparatuscomprising reading means and a member that are relatively movable,wherein the member carries a position track defined by a sequence ofalternative markings made in succession along the tape, wherein;

(a) the alternative markings record different values in a pseudo-randomsequence which is the result of repetitive operations on a seedconsisting of a small number of elements, the sequence having theproperty that a group of successive markings of length at least equal tothat of the seed occurs at a single position in the sequence so that asuccession of markings read from the track and of length at least equalto the seed defines an absolute position of the reading means and themember; and

(b) the reading means has at least three sensors arranged to respond todifferent locations within each marking with the pattern of the markingsand the location of the sensors arranged so that only a single sensorchanges state each time that the member moves through an interval ofdisplacement relatively to the sensing means, the states occurringconsecutively in alternative sequences along the member that arerecognizable by decoding logic fed with successive states as a logicalvalue corresponding to one of the alternative markings depending uponwhich sequence has been followed.

The term "alternative"as used herein does not exclude the possibilitythat the markings may be of three or more kinds, although two possiblemarkings are preferred because the sequences that are most convenientlyused are binary. The use of a number of sequence laid down end to endalong the member is also not excluded, but is not preferred. Thus in athree meter tape there could be three such sequences each one meter longfollowing one another.

The invention employs a member having marks and spaces defining at leastone encoded position track and sensing means arranged to detectdifferent locations of said at least one position track and to provideoutput signals at least one of whose states changes each time the memberhas travelled past the sensing means through an internal ofdisplacement, wherein the local states from the sensing means atsuccessive steps occur in sequences consecutively along the member andthat for each sequence are recognized by decoding logid fed withsuccessive local states as one or other logical value of an absoluteposition code (APC)for the member depending upon which sequence has beenfollowed

The data stream extracted from the local state sequence is used toprovide absolute position data, for this purpose a suitable codingsystem is needed. A set a cyclic codes known as maximum length binarysequences yields an appropriate code. These codes are long serial bitpatterns that are derived from all the possible combinations of a short,fixed length, section. They can be produced by certain autonomousfeedback shift registers from a binary seed of n-bits and have theproperties that(a) within any sequence any n-bit combination is uniqueand (b) the sequence is finite and is only (2^(n) -1) bits long. Thishas a particular benefit for the present purpose since if part of theoverall cyclic sequence, of length equal to the fixed length of thebinary seed, is examined, the position within the overall cyclic codecan be easily and uniquely deduced. Furthermore, this remains true nomatter where the section starts. Such pseudo-random sequences and theirproperties and their generation useing feedback shift registers arediscussed by F. Jessie MacWilliam et al. roc. IEEE,64, 1715-1729, 12Dec. 1976.

DESCRIPTION OF PREFERRED FEATURES

Given that every possible bit combination occurs somewhere in the cyclicAPC sequence code, then using the above approach yields no errorprotection. Errors that cause single or multiple bits to be corruptedcan cause very large positional errors since the positions on the tapefor these sequences are unlikely to be close to the uncorruptedsequence. There is an effective error detection and/or correctiontechnique that can be applied. Supposing the short section length forthe given cyclic code is n-bits then, as already stated, for everycombination of n-bits there will be a matching part of the cyclic codewhere n is the number of bits in the seed. However, supposing an (n+1 )bit section is examined, not every combination of (n+1 ) bit sequencesoccurs in the cyclic code. I.e. for a given n bit sequence, the (n+1 )is defined. For most single bit errors, the resulting n+1 bit sequencedoes not match any of the sequences in the cyclic code, thus giving ahigh degree of error direction.

The sequential state coding proposed herein has inherent error detectioncapabilities. Firstly, only a limited number of the possible localstates are allowed (any other seen is detected as an error) andsecondly, for each state there is usually only one, two or threeallowable transitions. The absolute position coding can also have errorprotection built in, as has been described, so the whole system candetect reading errors very reliably. The question then arises as to whatshould be done if an error is seen. The requirement for the user is thatunless an irrecoverable situation is reached the tape should readaccurately and normally. Supposing a local state sequence error is seen,then this is most likely to be the result of damage to the tape pattern.An appropriate course of action is to continue to observe local statetransitions until the next absolute position code bit is coded. Ifalternatively, an error in the absolute position code is found and it isnot within the error correction capability of the code, then the APC bitmust be discarded together with the accumulated APC bits and a new seedof APC bits must be read from the tape so that the new tape position canbe determined. Conveniently it is arranged that the decoding logic cansubstitute an expected APC bit for a first APC bit in error, but that asecond APC bit in error with the length n of the seed will trigger areset.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment of the invention will now be described, by way of exampleonly, with reference to the accompanying drawings, in which:

FIG. 1 is a diagram of a tape ruling having optical data capture fromencoder tracks and an associated data processing system providing adigital position output;

FIG 2. shows a short length of the tape rule;

FIG. 3 shows an analogue signal processing stage of the data processingsystem;

FIG. 4 is a diagram showing a sequence of allowed local output states ofthe signal processing stage and transitions between them within a singlesequence or block of tape absolute code (APC);

FIG. 5 is a block diagram of a local state input and decoder stage of adigital part of the data processing system;

FIG. 6 is a block diagram of a local state attribute register andcounter stage fed with output from the decoder stage of FIG 5;

FIG. 7 is a block diagram of decision logic operating on the value ofthe attribute registers and counters of FIG. 6 to provide decoded APCbits to subsequent APC decoding logic;

FIG. 8 shows state count logic providing a position output within acurrent local state sequence that is available to a microprocessorproviding a control and output portion of the data processing system;

FIG. 9 shows APC decision logic that controls the handling of APC databits fed from the local state decoding logic of FIGS. 5-8;

FIG. 10 shows a pseudo-random number generator forming an APC codegenerator stage of APC decoding logic; and

FIG. 11 shows a sensed APC bit shift register and comparator stageforming the remainder of the APC decoding logic.

DETAILED DESCRIPTION OF THE INVENTION

In the drawings, there is shown a steel tape rule that incorporates anelectronic system that can give a digital reading of length, measured ineither metric or imperial units. In use the tape operates in a similarmanner to a conventional steel rule but can include additional featuresto assist the user, for example, automatic correction of reading forreveal measurement, taking the tape body width into account.

The proposed measurement method is described below in conjunction withFIG. 1. A tape 1 of steel or other inextensible material is used as in aconventional tape rule controlled by a tensator spring 5 but is printedwith a pair of spatial encoded tracks 3, 4 in addition to the usualvisually readable distance scales 2. Internal to a casing 6 of theproduct, the tape 1 is illuminated by means of a light-emitting diode 31and image of the encoder tracks 3, 4 is formed using a lens 7 on aphotosensor array 30 which is arranged to have four sensitive areas ingrouped pairs corresponding to the paired encoder tracks 3, 4. Eachsensitive area views a small part of its encoder track. The pairs ofsensors in array 30 are aligned with the tracks 3, 4 which are definedby mark and space or black and white areas of varying widths, printed onthe tape 1, and image at the photosensors. Movement of the tape 1 causethe light level at each photosensor 30a (FIG. 3) to vary as the area ofThe tape 1 corresponding to an individual photosensitive area 30a changebetween black and white. By suitable analogue processing, four binarysignals, one for each photosensitive area 30a , are derived from thephotosensor outputs. The two states of the signals represent black orwhite at the areas on the tape 1 corresponding to each of thephotosensors. Movement of the tape 1 causes the binary signals to changeas the encoder tracks 3, 4 move past the photosensitive areas 30a.

The pattern of the encoder tracks 3, 4 and the spacing of thephotosensors 30a are arranged so that for every position on the tape 1,incremental movements of the tape 1 cause only one of the outputs tochange state at a time. Sequences of states fulfilling this criterionare known as Gray codes. Additionally, it can be arranged that thedirection of movement can, at all times, be deduced from the change inoutput states.

As is apparent from FIG. 1, the output of sensor array 30 is fed to ananalogue processing circuit 8 and then to CMOS digital processing logic9 which are implemented in a single application-specified integratedcircuit (ASIC) 10 that provides data at input port 11 of a 4-bit CMOSmask-programmed microprocessor 12 and receives information and commandsthrough an output port 13. The digital processing logic 9 of the ASIC 10includes a local state decoder and an APC binary sequence decoder thatare both implemented as logic and hence can run much more rapidly thanthe microprocessor 12 so that the code tracks 3, 4 can be followed evenduring rapid tape movement. The architecture of the microprocessor 12 issimilar to a conventional calculator-type microprocessor and the ports11, 13 communicate via a 4 -bit bus 15 with an ALU 16, accumulator 17,display RAM 18 and general purpose RAM 19 which may be of 2-2K size. Akeypad 21 communicates with the bus 15 through input port 20 that mayread up to 12 keys. The output value to be displayed is fed from displayRAM 18 to a display driver 22 that may conveniently drive a display ofup to 64 segments and is shown on a liquid crystal display 23.

ANALOGUE SIGNAL PROCESSING

The two encoder tracks 3, 4 as explained above, are read by fourphotosensors 30 that are illuminated either by a single light-emittingdiode 31 or by a pair of photodiodes 31 that illuminate a region of thetracks. In FIG. 3, only a single photosensor 30 is shown, but theremaining three channels closely resemble the channel illustrated. Eachphotosensor signal is passed through a respective signal conditionercomprising an amplifier 32, integrator 33 and comparator 34. The outputof integrator 33 is further fed to a 4 -channel peak detector 35 and theoutput of the channel having the highest signal level is fed throughattenuator 36 to a second input to comparator 34. The arrangement issuch that channels in which the signal level is close to the peak levelwithin the limit set by attenuator 36 will record logic 1 at 4-bit latch37 and channels with a lesser signal level will show a logic 0. The peakoutput of detector 35 is fed to a voltage controlled current source 38that controls the brightness of light-emitting diode 31. A timing andcontrol circuit 39 including an oscillator and latched gates providesenabling pulses at line 40 to the current source 38 to strobe thelight-emitting diode 31 and further provides a data ready pulse atoutput line 41 to instruct subsequent logic that the output of latch 37may be read. The use of pulses rather than a continuous output forlight-emitting diode 31 reduces power consumption, and the pulsingfrequency selected will be sufficiently rapid (e.g. 40 KHz) to allow thecode tracks to be read under normal conditions of use, as the tape isextended from and retracted into the housing. The peck detector 35 andattenuator 36 provides dynamic thresholding of the signal level at theinput to comparator 34 so that a binary output representing mark orspace (black or white) areas of the tape is continuously available.

LOCAL STATE DECODING

FIG. 4 shows a sequence of local states occurring in blocks eachdefining one bit of the absolute position code (APC) laid down along thetape and shows two alternative sequences by which the photosensors 30acan change in state from 0011 to 1100 and back again to 0011, thesequence reverting to its initial value of 0011 at the 8th transitionirrespective of which path is taken. It is to be understood that thepattern of mark and space markings defining the tracks 3, 4 will be laiddown end to end along the tape so as to implement the left hand or theright hand sequence of FIG. 4 with the initial 0011 state being commonto adjoining blocks. State changes are arranged to occur when the tape 1and photosensors 30 are moved relative to one another through aninterval of displacement and the pattern of marks and spaces iscomputer-generated and laid down along the tape 1 to implement therequired sequence of local states as viewed by the sensor array 30,changes between 0 and 1 of the four bit pattern commanding changes fromdark to light of the markings viewed by the respective sensors and thelengths of the individual dark and light markings. It will be noted thatthe successive transitions in each path conform to a Gray code in thateach differs from its neighbours by one bit only, and that each of thestates has a unique value, so that two successive states sensed by thephotosensor 30 give both the direction of tape movement and position inthe block. Thus successive output states of 0100 and 1100 uniquelydefine position 3 in a forward movement along the right hand pathdefining an APC bit φ whereas a transition from 0110 to 0111 uniquelydefines position 6 in a reverse tape movement along the left hand pathdefining an APC 1 bit. FIG. 2 shows a section of tape bearing markingscoded according to the above scheme. In FIG. 2 there is shown a patternof markings on the tape 1 that will obey the sequence of FIG. 4 whenread by an appropriately spaced and ordered sensor array. Each APC bitgives rise to one mark in each track 3, 4, and the marks occur indiagonally related pairs each roughly corresponding to one APC bit. Thecorrespondence is not exact, however, because neighbouring APC statesare conjoined and the dark markings are sometimes wholly within the spanof a single APC bit and sometimes extend across a boundary betweenadjoining APC bits so that the marking is common to adjacent bits. Eachmarking in a track 3 or 4 may be long (5 intervals of pitch), medium (4intervals of pitch) or short (3 intervals of pitch ) and the intervalsbetween adjacent markings may vary between 3 intervals of pitch in thecase of a pair of adjacent long markings and 5 intervals of pitch in thecase of a pair of short markings. Each APC 0 state may be perceived byeye as a diagonal pair of medium and short or short and short markingsin tracks 3, 4. Each APC 1 state may be perceived by the presence of amedium and long or by a long and long pair of diagonal markings in thetracks 3, 4. The markings are read by a set of four photosensor sittingsymmetrically over the tracks 3, 4 with the sensors being read clockwiseor anti-clockwise and with the pair of sensors reading each trackoccurring at three intervals of pitch. With this arrangement thesuccessive output states of the sensors as the tape 1 moves may becaused to obey FIG. 4, these properties arising by proper cooperationbetween the sensor array and the markings on the tape.

The outputs from termination and encoding logic in FIGS. 7 and 8 are asfollows:

(1) a "state count" indicating the number of state transitions recordedwithin a current APC block;

(2) an "APC clock" pulse indicating that a complete sequence of localstates has been traversed and a newly sensed APC bit has been decoded;

(3) a direction line 101, FIG. 7, indicating bit having a logic 1 valueif the tape is moving forward and a logic 0 value if it is movingbackwards;

(4) An APC bit line 108, FIG. 7 which can have the values 0, 1 or -1;

(5) an "APC Hlf" line 103, FIG 7, which is set (logic 1) if there is anequal probability that the APC bit being looked at is a 1 or a 0; and

(6) a minor error flag is set if there have been any erronioustransitions in a local state cycle.

The "state count" (1) is passed direct to the microprocessor 12 toindicate tape position within the currently sensed APC block and theremaining outputs are passed to APC decisions logic when the end of ablock has been reached. So the local state decoding logic has todetermine when a block has terminated and the attributes of the APC bitdecoded in that block.

Each local state transition seen within a local state block may be oneof five types:

(1) invalid: i.e. any transition that does not occur in FIG. 4;

(2) APC bit 1, forward;

(3) APC bit 1, backward;

(4) APC bit 0, forward;

(5) APC bit 0, backward.

Determination of the category into which a transition falls involvescomparison of the current state of the output latch 37 with its previousstates. In FIG. 5 a first clock phase φ1 and data ready line 41 areinputs to AND gate 56 whose output when high clocks current stateregister 54 so that when the data ready line 41 is active the outputs Q₀-Q₃ of the latch 37 are clocked by clock phase φ1 into the register 54.The previous state of register 54 is clocked by the output of AND gate56 into a last state register 55. At the same time, the values inregisters 54, 55 are clocked into decoding logic 57 that implements thelocal state transition diagram of FIG. 4 and derives therefrom a decodedAPC bit 0 or 1 according to whether the states in registers 54, 55 lieon the left-or-right hand side of the diagram of FIG. 4, that APC bitappearing at line 50 as a logic 0 or 1 output. Output line 51 providesan output bit significant of current tape direction (forward orbackward), output lines 52 provide a current position index within theAPC block and output line 53 provides an invalidity flag. Although gate56 is clocked at each phase φ1, the latch 58 does not change the outputstate at lines 50-53 unless comparator 59 indicates that the contents ofregisters 54, 55 are different, corresponding to tape movement betweenone local state and the next and enables the clock phase φ1 to pass viaAND gate 59a input to the clock in part to latch 58.

Referring to FIG. 6, logic is shown that operates principally in clockphases φ2 and φ3. Lines 51-53 communicate with a current attributeregister 70 that is clocked at phase φ3. But in the previous phase φ2the existing contents of register 70 are clocked into previous localposition register 60 and previous direction register 61 provided that asecond input to AND gate 71 from attribute register 70 indicates that avalid transition had been flagged in line 53. Clock phase φ2 alsoenables AND gate 89 to store previous consecutive valid transitions inregister 81 as will be more fully described below. On clock phase φ3, anumber of counters 75-80 are incremented or decremented or eitherdirectly in the case of transition counter 75 or via gates 82-87 in thecase of counters 76-80. Counter 76 is gated from lines 51 and 53 viagate 82 and records total valid forward transitions. Counter 77 isclocked through gate 83 from line 53 and line 51 with input inversionand records total valid backwards transitions. Counter 78 is gate viagate 84 from line 50, 53 and records total valid transitions within anexpected APC 1 bit: similarly counter 79 is gated via gate 85 from line53 and from line 50 with input inversion and records total validtransitions within an expected APC 0 bit. Counter 80 records consecutivevalid transitions within a given APC bit for a given direction. If theprevious direction continues on the next recognised APC bit exclusive ORgate 88 is enabled, clocked flip/flop 94 that provides an increment ordecrement input to counter 80 remains at its previous (high) state and avalid transition at the input to gate 87 enables clock phase φ3 to passto counter 80 thereby incrementing the number of valid counts. Ondirection change, exclusive OR gate 88 toggles flip/flop 94 and thecontents of counter 80 are now decremented at each clock phase φ3. If aninvalid count is flagged at line 53 or reset line 90 is activated, ORgate 93 resets the counter 80. A previous consecutive valid transistorsregister 81 is loaded from counter 80 on phase φ2 via AND gate 89 asmentioned above provided that the current bit in line 53 is invalid andthe output of counter 80 is not 0, control being via EXCLUSIVE OR gate95. In clock phase φ4 if the total forwards value in counter 76 equalsthe total backwards value in counter 77, exclusive OR gate 99 gives alow output to an inverting input of AND gate 91 which is fed via OD gate92 to reset line 90, thereby resetting all the counters and registers75-81 to their initial state. Resetting via OR gate 92 also takes placewhen system reset line 96 or encoding logic reset line 97 are active.

In FIG. 7 termination and encoding logic is applied to the contents ofthe counters 75-81 to determine when the end of a local state sequencehas ocurred and to provide an output for subsequent processing. Thevalues in counters 76, 77 provide inputs to comparator 100 whose outputat line 101 indicates tape forward movement (logic 1) or backwardsmovement (logic 0). The total valid APC 1 count and total valid APC 0count in registers 78, 79 are fed to comparator 102 which will give alogic 0 output except when the contents are equal; the output of gate102 is at line 103. If the output in line 103 is logic 0 the probabilityis that more than half of a local state cycle (APC bit) will have beendecoded correctly, and this is recognised in subsequent logic. If thecontents in APC 0 register 79 are zero as detected by a comparator 104and the contents of registers 78, 79 are equal as determined bycomparator 102, an output from comparator 104 and the output in line 103enable AND gate 105 to indicate a major error at line 106. An error flagin line 106 will be passed directed to the microprocessor 12 and willcause an error indication to be given on the display 12. The contents ofregister 78, 79 are fed to comparator 107 whose output in line 108indicates whether the APC bit being sensed is logic 1 or Logic 0.

Data in lines 101, 103, 106, 108 is fed to output latch 109, and theremainder of the logic of FIG. 7 is used to regulate whether that outputshould be made available for subsequent processing. According to a firstrule, if the current state is equal to the start state of a local statesequence and the consecutive valid transistors are greater than or equalto a threshold, then the output in latch 109 will be passed on.Accordingly, the current state in register 54 is fed to one input ofcomparator 110 whose other input is fed with a value equal to the startvalue of the local state sequence (in this instance 0011). The output ofcomparator 110 is fed to one input of AND gate 111 whose other output isfed with the contents of consecutive transistors counter 80 throughthreshold comparator 112. If both inputs to gate 111 are high, a logic 1output is fed to OR gate 113 that in turn enables AND gate 114 to clockthe latch 109 at the next clock phase φ5 thereby latching the statecount outputs into latch or buffer 109. According to a second rule, theoutput latch 109 will be clocked on φ5 via OR gate 113 and And gate 114if the following four conditions apply:

(a) the contents of previous consecutive valid transistors counter 81exceed a threshold set by comparator 115;

(b) the valid line 53 is set;

(c) the current direction is the same as the previous valid direction asindicated at input line 116 from comparator 88; and

(d) the current index in line 52 is less than a previous valid indexheld in register 60 as determined by comparator 118.

When the above four conditions are satisfied the output at gate 117 goesto logic 1. The object of this rule is to take account of sensing errorsat the boundaries of state blocks resulting in failure to recognise thatthe last block has ended and a new block is being sensed.

According to a third rule, if the current index equals the previouslyvalid index and equals zero (indicating no tape movement) and the numberof transitions represents adjacency to the end of a cycle (7 transitionsin this instance) then gates 113, 114 clock the output latch 109.Accordingly the following conditions must apply:

(a) the value in transition count register 75 fed through threshold (>7)detector 119 provides an enabling input to AND gate 120; and

(b) the contents of previously valid index register 60 and current indexin line 52 are both equal to 0 as determined by comparator 121 giving anenabling input to AND gate 120.

The effect of the third rule is to bring about a transition independentof an error at the end of a block.

FIG. (8) shows state count logic that identifies the position of thecounters within the currently read APC state sequence based on apreviously valid index in position register 60 and a previously validdirection in direction register 61. An accumulator 62 is clocked atclock phase φ3 to load the value of previously valid index fromregisters 60 and on clock phase φ4 the value in accumulator 62 isincremented by 1. On clock phase φ5 the new value in accumulator 62 isloaded into latch 63 as a state count output available to themicroprocessor 12 together, with tape direction from register 61.Accordingly a current tape position within the local state sequencebeing read is available to the microprocessor 12 to give finepositioning of the tape 1.

It follows therefore that the local state decoding stage of the digitalprocessing logic 9 supplies a local state count output for directprocessing by the microprocessor 12 together with an APC bit, tapedirection and error flag information to subsequent APC decoding logicforming part of the digital processing logic 9.

THE APC-DECODING LOGIC

The APC decoding logic of FIGS. 9-11 receives APC bit information fromthe local encoding logic of FIGS. 5-8, and assembles successive APC bitsinto a n-bit APC word which in the present instance is eleven bits longand is stored in a shift register n-bits long clocked on detection ofeach APC bit. It contains an APC code generator that when clocked froman initial state reproduces the sequence of APC bits laid down on thetape, a comparator for determining a match of the state of the APC codegenerator with that of the sensed APC word shift register, and a counterfor indicating how many register clock pulses are required to achieve amatch, the value in the counter being significant of position in the APCsequence and hence of tape position.

Means are provided for initialisation and rapid clocking of the codegenerator until a match is obtained, followed by clocking on successiveincoming APC bits so that the bit pattern in the APC word shift registeris tracked by the state of the APC code generator. Error checking isprovided by a "look ahead" facility in which an incoming APC bit iscompared with an expected APC bit from the APC code generator and anerror is flagged if a match is not obtained.

The circuit of FIG. 9 controls the processing of APC data fed via latch109 and toggles between a normal mode in which a clock pulse isgenerated on a pseudo-random bit generator (PRBG) clock line on everyAPC bit, and a reset mode in which sequential APC bits are counted toenable tape position to be recalculated. In an error condition, OR gate130 receives an input from APC half-bit output line 103 through latch109 or an invalid APC bit from line 129 (FIG. 11) indicating either thatthe local state logic has been unable to decode a local state sequenceor that the APC bit from the local state logic is not the expected nextbit in the APC sequence.

In either of these events, output of OR gate 130 goes high and isclocked on the next system clock through latch 131 to a reset line 132.The line 132 also goes high if a reset signal is received from themicroprocessor 12 via line 133 and output port 13. The state of resetline 132 is fed through OR gate 134 to reset an n-bit counter 135. Theerror signalled at line 132 clocks latch 136 to cause a bad APC line 137to go low and the state on line 137 is also fed to one input of adirection match OR gate 138 whose other input from line 101 is at logic1 when the tape is going forward, the direction output from gate 138being at line 139.

The value on line 101 is also fed into latch 140 the contents of whichare put out at line 141 when an APC clock signal of phase φ3 occurs inline 142. The forward direction at line 101 and last forward directionat line 141 are compared at EXCLUSIVE OR gate 143 and if different causedirection change line 144 to be set. The direction change signal at line144 is also inverted and fed to AND gate 145 whose other input is theAPC clock phase φ3 and whose output goes to the clock input counter 135.The direction of count is governed by the value in lines 101, 146 sothat when the signal at line 146 is high, the counter 135 counts in apositive sense and when the signal is low, counts in a negative sense.The shift register counter 135 has outputs >11 or <-11 (depending uponthe state of line 146), which form inputs to OR gate 147 which clockslatch 149 via line 148. The input to latch 149 is a constant logic 1.The input to latch 136 is a constant logic 0. Latches 136, 149 areenabled via line 150 which is an output of AND gate 151. The inputs toAND gate 151 are a comparator input 152 (FIG. 11) and a "get match"output 153 from latch 149. Assuming that the value in the PRBG shiftregister 164 is not the same as the value in the APC shift register 184,then comparator line 152 will be high, the "get match" line 153 willalso be set high and line 150 will further be high, enabling latches149, 136. The outputs of latches 149, 136 are fed as inverting andnormal inputs to gate 154 fed with system clock pulses at 155 whichappear at output line 156 as an input to OR gate 157. Accordingly in anerror condition the system clock equals the pseudo-random-bit generator(PRBG) clock 158. In a non-error state line 137 is set to logic 1 whichenables the APC clock phase T3 at line 142 to be passed through AND gate159, output line 160, and OR gate 157 so that the APC clock at line 142provides the PRBG clock 158. Accordingly the decision logic toggles theoutput at line 158 between an error state in which fast system clockpulses from line 155 appear and a normal mode in which a clock pulseappears when an APC bit has been decoded as indicated by a pulse in line142.

FIG. 10 shows a pseudo-random bit or number generator for generatingwithin the digital processing circuitry a sequence of pseudo-randomnumbers corresponding to the APC bit sequence on the tape. It may becontrolled according to the direction of movement of the tape togenerate the APC bit which is above or below the current APC positionand generates an APC count corresponding to the position of the APCsequence in the pseudo-random number sequence. PRBG clock pulses at line158 are connected to APC up/down counter 161 which counts in a sensetoggled by direction line 101. The clock line 158 and direction changeline 144 are input into gate 162 whose output in line 163 provides aclock into an n-bit shift register 164 whose direction of clocking isset by direction line 101 and that can be reset via line 132 (FIG. 9).The shift register has inputs 169, 170 and taps are taken atintermediate positions 165-168. Taps 165, 167 form an input to EXCLUSIVEOR gate 171 whose output provides input 169 to shift register 164. Taps166, 168 form an input to EXCLUSIVE OR gate 172 whose output providesinput 170 to the shift register 164. This combination of taps and gatesis selected to generate an appropriate pseudo-random sequence. Taps 166,170 form an input to selector 173 whose output 174 depends on the stateof the match direction value in line 139. Thus in normal operation line139 changes state between forwards and reverse tape travel, but undererror conditions the line 139 is held to logic 0 so that the selectors173, 176 are set to look at tabs of the shift register 164 correspondingto forward movement. Similarly taps 169, 175 from the shift registerform an input to selector 176 whose output 177 depends upon the matchdirection value in line 139. The bits in output lines 174, 177 fromselectors 173, 176 are the expected next forward and reverse bits in theAPC sequence. Thus the register 164 acts as a decoder for the APC codeon the tape 1 (that will have been generated by similar clocked shiftregister acting as an encoder) and provides a "look ahead" facility.

FIG. 11 shows how detected APC bits are gathered for comparison. Theexpected APC bits at 174, 177 are fed to selector 182 controlled by thesignal in line 101 and one of them is passed as an output in line 181.The forward bit (bit f) in line 174 is output if line 101 is high,otherwise the backwards bit (bit b) in line 177 is output. The expectedAPC bit in line 181 forms one input to selector 180 whose other inputbit is the decoded APC bit at line 108. Selector 180 is controlled bybad APC signal line 137 to pass the expected bit 181 to line 183 undernormal conditions, thereby allowing a decoded APC shift register 184 toignore errors in decoding single APC bits, or the decoded bit in line108 during the reset condition when accumulating a new APC code. Thedetected or substituted APC code bits at 183 are fed successively intoand through the n-bit shift register 184 which accumulates an APC wordconsisting of the last n decoded or substituted APC bits (in thisinstance n=11). EXCLUSIVE OR gate 185 compares the expected APC bit at181 with the decoded bit at 108. If they are both the same, output 186of gate 185 stays low but if they are different then output 186 of gate185 goes high. In the absence of an APC hlf signal the signal in line103 which forms an inverting input to AND gate 187 is low. The input togate 187 from line 186 will remain low while there is a match betweenthe expected and decoded APC bits and the output 188 of the gate 187will remain low: otherwise lines 186 and 188 go high indicating amismatch in the expected and encoded APC bits. If the APC half line 103is high indicating uncertainty in the APC bit from the local statedecoding the line 188 will remain low irrespective of the state of line186. A mismatch in decoded and expected APC bits detected at gate 185will set a latch 202 (described below) to indicate a 1-bit error andwill start clocking of an error counter 207.

An inverted direction change signal at direction change line 144 and APCCLK signals of phase T2 in line 192 form inputs to AND gate 191 so thatAPC clock pulses are passed to line 190 when line 144 is set low. Whendirection change input line 144 is low the APC CLK signals of phase T2appear on clock input 195 of shift register 184. The signals on line188, 190 are combined at AND gate 189 whose output line 201 will alsocarry an APC CLK signal of phase T2 provided that (i) the APC hlf line103 remains low, (ii) the direction change line 144 remains low and(iii) the lines 186 and 188 have gone high, indicating that the expectedand decoded APC bits differ.

APC CLK pulses of phase T2 in output line 201 of AND gate 189 appear asa clock input to latch 202 and an input to AND gate 203. The effect ofthe APC CLK pulses in line 201 is (a) to set the output 220 of latch 202that has a logic 1 input high when line 201 goes high, and (b) where ANDgate 203 is enabled through line 220 to pass to the invalid APC line129.

When a first erroneous APC bit is detected, an error counter 207 iscleared and set to count through a set of the next n APC bits so thattrack is kept of the substituted APC bit in relation to the sequencebeing built up in the shift register 184. When there has been no tapedirection change and the direction change line 144 that provides aninverting input to AND gate 216 is low, the gate 216 passes APC CLKpulses of phase T1 carried by line 217, and the clock pulses are carriedby output line 215 to AND gate 213. Output 212 of AND gate 213 carries aclock when input 215 to gate 213 carries the APC CLK pulses of phase T1.

Input 214 of AND gate 213 will have been latched high by latch 202signifying an APC bit in error. If a decoded APC bit is or was in errorand the consequent substituted APC bit is one of the n APC bits presentin shift register 184, the error counter 207 will be clocked by APC CLKpulses of phase T1 as every decoded APC bit is generated. If the tapedirection input at line 101 to counter 207 is low then the count incounter 207 is decremented for every clock pulse, but if line 101 ishigh, then the count at counter 207 is incremented. If the count incounter 207 reaches n or -n, then output 230 or output 231 are set high,these lines providing inputs to OR gate 210. When either of lines 230 or231 goes high, the output line 211 of OR gate 210 is also set high, thatline providing a logic 1 input to OR gate 204 so that the output line208 goes high and resets the error counter 207 to zero through OR gate204 that also passes a reset signal on line 132. Therefore if a decodedAPC bit did not match the expected value in either forward or reversetape travel, the expected APC bit has been fed into shift register 184in substitution for the erroneously decoded bit, and by subsequent tapemovement the substituted bit has been clocked out of the shift register184 by n consecutive clock pulses then the error counter 207 is reset tozero. The high value of line 211 is also input to OR gate 221 whoseoutput line goes high and resets latch 202. (The other input to OR gate221 is via reset line 132). The consequent low output in line 220 fromlatch 202 is input via line 214 to AND gate 213 which now will nottransmit APC CLK pulses of phase T1 to counter 207. And gate 203 is alsodisabled because its input at line 220 is low, and APC CLK pulses ofphase T2 can no longer pass to line 129. Consequently an erroneousdecoded APC bit can be substituted with an expected APC bit and then-bit APC code in shift register 184 will be preserved provided that thenext n decoded APC bits match their expected values. No output willappear at the invalid APC line 129 on a first invalid APC bit becauseoutput 220 of latch 202 will be low during the relevant APC clock pulseof phase T2. But the circuit of FIG. 11 responds to a second erroneousAPC bit within a word of n APC bits by outputting an invalid APC flag atline 129 which forces the system to reset. If a previous error has beendetected and the substituted APC bit is still in shift register 184, theoutput line 220 of latch 202 is set high and enables AND gate 203. If asecond error occurs, input line 201 to AND gate 203 goes high again,setting the invalid APC output line 129 high and forcing the system intoreset. In this way the circuit of FIG. 11 can recover from a single APCbit error in an n-bit sequence but will reset if a second error hasoccurred in the same sequence, causing a reset in the decision logic ofFIG. 9.

Assuming no direction change at 144, incoming APC CLK pulses of phase T2at line 192 pass via AND gate 191 and line 190 to the clock input 195 ofthe shift register 184 whose n-APC sensed bit output at lines 196 formsone input to comparator 197 whose other input 200 is the current valueof the generated APC code in shift register 164. The output line 152from comparator 157 is low when the generated APC code in decoder orPRBG shift register 164 matches the sequence of sensed and decoded APCbits in register 184 and provides an input to gate 151 that toggles theclock pulses at line 158 between system clocking from line 155 and APCclocking from line 142. Thereby the APC decoding shift register 164 isclocked rapidly by system clock pulses until a match is obtained andthereafter, provided that the match at comparator 197 is maintainedchanges state only with incoming APC bits.

Assuming that valid transitions have been sensed at both the local stateand APC levels, the state count output in latch 63 and the value in APCcounter 161 are available through input port 11 to the microprocessor 12where they are combined by a position analysis program to derive theposition of the tape 1 relative to the casing 6, which position isoutput through display RAM 18 to the liquid crystal display 23.

We claim:
 1. Displacement measuring apparatus comprising reading meansand a member moveable relative to the reading means, said membercarrying a position track defined by a sequence of alternative markingsmade in succession along the member,the alternative markings recordingdifferent values in a pseudo-random sequence which is the result ofrepetitive operations on a seed consisting of a small number of elementsand is at least a portion of a linear binary sequence obtained byclocking a feedback shift register, the sequence having the propertythat a group of successive markings of length at least equal to that ofthe seed occurs at a single position in the sequence so that asuccession of markings read from the track and of length at least equalto the seed defines an absolute position of the reading means and themember; said reading means having at least three sensors arranged torespond to different locations within each marking with the pattern ofthe markings and the location of the sensors arranged so that only asingle sensor changes state each time that the member moves through aninterval of displacement relatively to the sensing means, the statesoccurring consecutively in alternative sequences along the member thatare recognizable by decoding logic fed with successive states as alogical value corresponding to one of the alternative markings dependingupon which sequence has been followed, said decoding logiccomprising:first shift register means having a length at least equal tothe seed through which logical values are clocked, said valuescorresponding to successive markings recognized by the reading means,second shift register means for reproducing the pseudo-random sequencewhen the register means are clocked; and comparator means for detectinga relationship in the states of the first and second shift registermeans.
 2. An image reading device according to claim 1, furthercomprising a stopper means for stopping said retaining member fromrotating to a position where said member would become detachable, saiddetachable position being one in which the planes of said rotary fulcrumshaft are parallel to a center line of said guide portions of saidmounting recesses.
 3. An image reading device comprising:a device body;a document transport means which is provided within said device body andwhich transports original documents along a predetermined documenttransport path; an image sensor unit which is located under saiddocument transport path so as to read each of the documents passingthrough said path; a retaining member rotatably mounting said imagesensor unit to said device body for rotation relative to said devicebody, said retaining member comprising a rotary fulcrum shaft locatedadjacent to a bottom of said device body; and a cover member forswingingly covering a portion of said bottom of said device body nearthe position where said retaining member is located, said cover memberincluding a means for restricting the rotational angle through whichsaid image sensor unit can rotate when said cover member is fixedlymounted in place covering said portion of said bottom of said devicebody.
 4. Apparatus according to claim 1 wherein the decoding logicsupplies a local state count significantly of the position of the memberwithin a currently sensed marking which can be used to indicate a fineposition of the member between recognized markings.
 5. Apparatusaccording to claim 1 wherein the decoding logic includesmeans responsiveto the output state of the comparator means for rapidly clocking thesecond shift register means until the relationship is detected and,while the relationship exists, clocking the first and second shiftregisters to recognize logical values corresponding to the markings; andcounter means for counting the clock pulses fed to the second shiftregister means.
 6. Apparatus according to claim 1 wherein the decodinglogic includes direction control logic for recognizing a direction ofrelative movement of the reading means and member from successive statesof said sensors and, depending upon said recognized direction ofmovement, for altering the direction in which said counter means counts.7. Apparatus according to claim 1, wherein the states of each sequencedefine a binary code in which each state differs from its neighbors sothat a transition between a pair of adjacent states defines the logicalvalue of a marking, as well as the positions in the state sequencebetween which the transition has occurred and the direction in which thenumber has moved, the decoding logic includes a current local stateregister means and last local state register means into which sensedstates are fed in pairs, the values in said current and said last localstate register means being fed to decoder means that serves to decodesaid local states and provide outputs defining whether the successivelocal states define a valid local state transition, an index within thestate sequence, the direction of travel of the member and the markingcorresponding to that transition.
 8. Apparatus according to claim 7,wherein the decoding logic(a) counts forward and backward transitions ina sequence being read and provides a difference output significant ofthe direction of the member and the distance moved; (b) counttransitions having logic 1 and logic 0 values of the marking and outputsa decoded absolute marking value depending on the difference in saidcounts; and (c) flags when an error has occurred in a sensed local statesequence.
 9. Apparatus according to claim 8, wherein the decoding logicflags when there is a half probability that the local state sequence hasbeen decoded correctly, the logical value corresponding to the expectedmarking being admitted to the first shift register means without anerror being flagged.